This invention relates to systems for hard wiring information into integrated circuit elements and in particular to such systems when utilised in data processing apparatus using large scale integrated circuit (LSI) chips or elements.
In data processing apparatus which includes a number of such chips it is often necessary to hard wire certain information into the chips by making selected external connections to the chips. For example, in a system including a number of identical memory chips, each chip may be provided with a unique identifying address by hard wiring predetermined numbers into the units. In known systems, hard wiring-in of information has been performed by providing each chip with a number of terminals, one for each bit of information which is to be hard wired-in. Each of these terminals is connected selectively either to a D.C. voltage source representing the binary digit "1", or to a D.C. voltage source representing the digit "0". Thus, for example, if an eight-bit address is to be hard wired into a chip, the chip must be provided with eight terminals specifically for this purpose.
This technique uses a large number of terminals, which is a disadvantage for an LSI chip, since the cost of the chip increases steeply as the number of terminals on the chip increases.